Full-rate and sub-rate clock can be output for synchronized testing
Trigger output provides programmable trigger states based on BER and the link training state machine
- Software Control Interface
Controlling software can be installed on any PC through a USB interface
- PCI Express 3.0 Clock Multiplier
PeRT3 has a built-in PCIe Ref Clock input for synchronizing to a PCI Express 3.0 system’s master clock for receiver testing
MHz Ref clock allows multiple PeRT3 systems to be synchronized for multi-channel testing
